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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICH_LR&lt;n&gt;, List Registers, n = 0 - 15</h1><p>The GICH_LR&lt;n&gt; characteristics are:</p><h2>Purpose</h2>
        <p>These registers provide context information for the virtual CPU interface.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_GICv3_LEGACY is implemented and EL2 is implemented. Otherwise, direct accesses to GICH_LR&lt;n&gt; are <span class="arm-defined-word">RES0</span>.</p>
        <p>This register is available when the GIC implementation supports interrupt virtualization.</p>

      
        <p>A maximum of 16 List registers can be provided. <a href="ext-gich_vtr.html">GICH_VTR</a>.ListRegs defines the number implemented. Unimplemented List registers are RAZ/WI.</p>
      <h2>Attributes</h2>
        <p>GICH_LR&lt;n&gt; is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_31">HW</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_30">Group</a></td><td class="lr" colspan="2"><a href="#fieldset_0-29_28">State</a></td><td class="lr" colspan="5"><a href="#fieldset_0-27_23">Priority</a></td><td class="lr" colspan="3"><a href="#fieldset_0-22_20">RES0</a></td><td class="lr" colspan="10"><a href="#fieldset_0-19_10">pINTID</a></td><td class="lr" colspan="10"><a href="#fieldset_0-9_0">vINTID</a></td></tr></tbody></table><h4 id="fieldset_0-31_31">HW, bit [31]</h4><div class="field">
      <p>Indicates whether this virtual interrupt is a hardware interrupt, meaning that it corresponds to a physical interrupt. Deactivation of the virtual interrupt also causes the deactivation of the physical interrupt corresponding to the INTID:</p>
    <table class="valuetable"><tr><th>HW</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This interrupt is triggered entirely in software. No notification is sent to the Distributor when the virtual interrupt is deactivated.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>A hardware interrupt. A deactivate interrupt request is sent to the Distributor when the virtual interrupt is deactivated, using GICH_LR&lt;n&gt;.pINTID to indicate the physical interrupt identifier.</p>
<p>If <a href="ext-gicv_ctlr.html">GICV_CTLR</a>.EOImode == 0, this request corresponds to a write to <a href="ext-gicv_eoir.html">GICV_EOIR</a> or <a href="ext-gicv_aeoir.html">GICV_AEOIR</a>, otherwise it corresponds to a write to <a href="ext-gicv_dir.html">GICV_DIR</a>.</p></td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-30_30">Group, bit [30]</h4><div class="field">
      <p>Indicates whether the interrupt is Group 0 or Group 1:</p>
    <table class="valuetable"><tr><th>Group</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Group 0 virtual interrupt. <a href="ext-gicv_ctlr.html">GICV_CTLR</a>.FIQEn determines whether it is signaled as a virtual IRQ or as a virtual FIQ, and <a href="ext-gicv_ctlr.html">GICV_CTLR</a>.EnableGrp0 enables signaling of this interrupt to the virtual machine.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Group 1 virtual interrupt, signaled as a virtual IRQ. <a href="ext-gicv_ctlr.html">GICV_CTLR</a>.EnableGrp1 enables signaling of this interrupt to the virtual machine.</p>
        </td></tr></table>
      <div class="note"><span class="note-header">Note</span>
        <p><a href="ext-gicv_ctlr.html">GICV_CTLR</a>.CBPR controls whether <a href="ext-gicv_bpr.html">GICV_BPR</a> or <a href="ext-gicv_abpr.html">GICV_ABPR</a> determines if a pending Group 1 interrupt has sufficient priority to preempt current execution.</p>
      </div>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-29_28">State, bits [29:28]</h4><div class="field">
      <p>The state of the interrupt. This field has one of the following values:</p>
    <table class="valuetable"><tr><th>State</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Inactive</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p>Pending</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>Active</p>
        </td></tr><tr><td class="bitfield">0b11</td><td>
          <p>Active and pending</p>
        </td></tr></table><p>The GIC updates these state bits as virtual interrupts proceed through the interrupt life cycle. Entries in the inactive state are ignored, except for the purpose of generating virtual maintenance interrupts.</p>
<div class="note"><span class="note-header">Note</span><p>For hardware interrupts, the active and pending state is held in the Distributor rather than the virtual CPU interface. A hypervisor must only use the active and pending state for software originated interrupts, which are typically associated with virtual devices, or for SGIs.</p></div><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-27_23">Priority, bits [27:23]</h4><div class="field">
      <p>The priority of this interrupt.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-22_20">Bits [22:20]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-19_10">pINTID, bits [19:10]</h4><div class="field"><p>The function of this field depends on the value of GICH_LR&lt;n&gt;.HW.</p>
<p>When GICH_LR&lt;n&gt;.HW == 0:</p>
<ul>
<li>Bit [19] indicates whether the interrupt triggers an EOI maintenance interrupt. If this bit is 1, then when the interrupt identified by vINTID is deactivated, an EOI maintenance interrupt is asserted.
</li><li>Bits [18:13] are reserved, SBZ.
</li><li>If the vINTID field value corresponds to an SGI (that is, 0-15), bits [12:10] contain the number of the requesting PE. This appears in the corresponding field of <a href="ext-gicv_iar.html">GICV_IAR</a> or <a href="ext-gicv_aiar.html">GICV_AIAR</a>. If the vINTID field value is not 0-15, this field must be cleared to 0.
</li></ul>
<p>When GICH_LR&lt;n&gt;.HW == 1:</p>
<ul>
<li>This field indicates the pINTID that the hypervisor forwards to the Distributor. This field is only required to implement enough bits to hold a valid value for the ID configuration. Any unused higher order bits are RAZ/WI.
</li><li>If the value of pINTID is 0-15 or 1020-1023, behavior is <span class="arm-defined-word">UNPREDICTABLE</span>. If the value of pINTID is 16-31, this field applies to the PPI associated with this same PE as the virtual CPU interface requesting the deactivation.
</li></ul><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-9_0">vINTID, bits [9:0]</h4><div class="field">
      <p>This INTID is returned to the VM when the interrupt is acknowledged through <a href="ext-gicv_iar.html">GICV_IAR</a>. Each valid interrupt stored in the List registers must have a unique vINTID for that virtual CPU interface. If the value of vINTID is 1020-1023, behavior is <span class="arm-defined-word">UNPREDICTABLE</span>.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing GICH_LR&lt;n&gt;</h2>
        <p>This register is used only when System register access is not enabled. When System register access is enabled:</p>

      
        <ul>
<li>For AArch32 implementations, <a href="AArch32-ich_lrn.html">ICH_LR&lt;n&gt;</a> provides equivalent functionality.
</li><li>For AArch64 implementations, <a href="AArch64-ich_lrn_el2.html">ICH_LR&lt;n&gt;_EL2</a> provides equivalent functionality.
</li></ul>
      <h4>GICH_LR&lt;n&gt; can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC Virtual interface control</td><td><span class="hexnumber">0x0100</span> + (4 * n)</td><td>GICH_LR&lt;n&gt;</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When GICD_CTLR.DS == 0, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When an access is Secure, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When an access is Non-secure, accesses to this register are <span class="access_level">RW</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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